From 939e36de194b4d1b6cea5e561f0e208950400a71 Mon Sep 17 00:00:00 2001
From: Ziyang Hu <hu.ziyang@cantab.net>
Date: Thu, 14 Jul 2022 17:54:15 +0800
Subject: [PATCH] fix component logic

---
 src/data/tx_triple.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/data/tx_triple.rs b/src/data/tx_triple.rs
index 84ebfb53..efd566ba 100644
--- a/src/data/tx_triple.rs
+++ b/src/data/tx_triple.rs
@@ -546,6 +546,10 @@ impl SessionTx {
             for (attr, v) in pairs {
                 self.parse_tx_request_inner(eid, &attr, v, action, since, temp_id_ctx, collected)?;
             }
+        } else if !eid.is_perm() {
+            for (attr, v) in pairs {
+                self.parse_tx_request_inner(eid, &attr, v, action, since, temp_id_ctx, collected)?;
+            }
         }
         Ok((eid, has_unique_attr))
     }